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| Datasheet File OCR Text: |
| september 2013 doc id 18260 rev 5 1/68 1 l99dz80ep door actuator driver features one full bridge for 6 a load (r on = 150 m ) two half bridges for 3 a load (r on = 300 m ) two half bridges for 0.5 a load (r on = 1600 m ) one high-side driver for 5 a load (r on = 100 m ) one configurable high-side driver for up to 1.5 a (r on = 500 m ) or 0.35 a (r on = 1600 m ) load one configurable high-side driver for 0.7 a (r on = 800 m ) or 0.35 a (r on = 1600 m ) load two high-side drivers for 0.5 a load (r on = 1600 m ) programmable softstart function to drive loads with higher inrush currents as current limitation value very low v s current consumption in standby mode (i s < 6 a typ; t j 85 c) current monitor output for all high-side drivers central two-stage charge pump motor bridge driver with full r dson down to 6 v device contains temperature warning and protection open-load detection for all outputs overcurrent protection for all outputs separated half bridges for door lock motor programmable pwm control of all outputs stm standard serial peripheral interface (st- spi 3.1) control block for electrochromic element electrochromic element can be negatively discharged prepared for additional fail-safe path for h-bridge applications door actuator driver with 6 bridges for double door lock control, mirror fold and mirror axis control, high-side driver for mirror defroster, bulbs and leds. control block with external mos transistor for charging / discharging of electrochromic glass. motor bridge driver. h-bridge control for external power transistors description the l99dz80ep is a microcontroller driven multifunctional door actuator driver for automotive applications. up to five dc motors and five grounded resistive loads can be driven with six half bridges and five high-side drivers. four external mos transistors in bridge configuration can be driven. an electrochromic mirror glass can be controlled using the integrated spi-driven module in conjunction with an external mos transistor. the mirror glass can also be discharged through a negative supply. the integrated spi controls all operating modes (forward, reverse, brake and high impedance). also all diagnostic information is available via spi read. table 1. device summary package order codes tray tape and reel tqfp-64 l99dz80ep L99DZ80EPTR * $ 3 * & ) 7 tqfp-64 www.st.com
contents l99dz80ep 2/68 doc id 18260 rev 5 contents 1 block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 2.2 esd protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.3 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.4 package and pcb thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.4.1 tqfp-64 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.5 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.6 outputs out1 - out11, ecv, ecfd . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.7 h-bridge driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.8 electrochrome mirror driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.9 spi / logic ? electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.1 dual power supply: vs and vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.2 wake up and active mode/standby mode . . . . . . . . . . . . . . . . . . . . . . . . 32 3.3 charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.4 diagnostic functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.5 overvoltage and undervoltage detection at vs . . . . . . . . . . . . . . . . . . . . 32 3.6 overvoltage and undervoltage detection at vcc . . . . . . . . . . . . . . . . . . . 33 3.7 temperature warning and shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.8 inductive loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.9 open-load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.10 overcurrent detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.11 current monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.12 pwm mode of the power outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.13 cross-current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.14 programmable soft-start function to drive loads with higher inrush current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.15 h-bridge control (dir, pwmh, bits sd, sds) . . . . . . . . . . . . . . . . . . . . . 36 3.16 h-bridge driver slew-rate control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 l99dz80ep contents doc id 18260 rev 5 3/68 3.17 resistive low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.18 short circuit detection/drain source monitoring . . . . . . . . . . . . . . . . . . . . 38 3.19 h-bridge monitoring in off-mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.20 programmable cross current protection . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.21 controller of electrochromic glass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.22 watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4 functional description of the spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.1.1 chip select not (csn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.1.2 serial data in (di) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.1.3 serial clock (clk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.1.4 serial data out (do) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.1.5 spi communication flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.2 command byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.2.1 operation code definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.3 device memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5 spi - control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.1 control register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 5.2 control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 5.3 control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5.4 control register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5.5 control register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 5.6 control register 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 5.7 control register 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 5.8 configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 5.9 status register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 5.10 status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 5.11 status register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 5.12 status register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6 package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 6.1 ecopack ? package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 6.2 tqfp-64 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 contents l99dz80ep 4/68 doc id 18260 rev 5 6.3 tqfp-64 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 7 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 l99dz80ep list of tables doc id 18260 rev 5 5/68 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 3. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 4. esd protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 5. operating junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 6. temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 7. package thermal impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 8. supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 9. overvoltage and undervoltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 10. current monitor output (cm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 11. charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 12. on-resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 13. power outputs switching times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 14. current monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 15. gate drivers for the external power-mos (h-bridge) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 16. gate drivers for the external power-mos switching times . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 17. drain source monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 18. open-load monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 19. electrochrome mirror driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 20. delay time from standby to active mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 21. inputs: di, csn, clk, dir and pwmh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 22. ac-characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 23. dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 24. watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 25. h-bridge control truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 26. h-bridge ds-monitor threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 27. cross-current protection time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 28. command byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 29. operation code definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 30. ram memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 31. rom memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 32. global status byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 33. control register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 34. control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 35. control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 36. control register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 37. control register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 38. control register 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 39. control register 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 40. configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 41. status register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 42. status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 43. status register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 44. status register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 45. tqfp-64 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 46. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 list of figures l99dz80ep 6/68 doc id 18260 rev 5 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 2. pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 3. tqfp-64 2 layer pcb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 4. tqfp-64 4 layer pcb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 5. tqfp-64 thermal impedance junction to ambient vs pcb copper area . . . . . . . . . . . . . . . 14 figure 6. ighxr ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 7. ighxf ranges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 8. h-driver delay times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 9. spi timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 10. spi input and output timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 0 figure 11. spi delay description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 12. power-output (out<11:1>, ecv, ecfd) timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 13. overcurrent recovery mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 14. h-bridge gshx slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 15. h-bridge diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 16. h-bridge open-load detection (no open-load detected) . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 17. h-bridge open-load detection (open-load detected) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 18. h-bridge open-load detection (short to ground detected) . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 19. h-bridge open-load detection with h-olth high = ?1? (short to v s detected) . . . . . . . . . 41 figure 20. electrochrome mirror driver with mirror referenced to ground . . . . . . . . . . . . . . . . . . . . . . 43 figure 21. electrochrome mirror driver with mirror referenced to ecfd for negative discharge . . . . . 44 figure 22. write and read spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 23. tqfp-64 package dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 24. tqfp-64 power lead-less tray shipment (no suffix) (part 1) . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 25. tqfp-64 power lead-less tray shipment (no suffix) (part 2) . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 26. tqfp-64 power lead-less tape and reel shipment (suffix ?tr?) (part 1). . . . . . . . . . . . . . . 63 figure 27. tqfp-64 power lead-less tape and reel shipment (suffix ?tr?) (part 2). . . . . . . . . . . . . . . 64 l99dz80ep block diagram and pin description doc id 18260 rev 5 7/68 1 block diagram and pin description figure 1. block diagram ' u l y h u , q w h u i d f h / r j l f ' l d j q r v w l f 0 6 3 , , q w h u i d f h 7 2 : d w f k g r j & k d u j h 3 x p s & 0 & 6 1 & / . ' 2 ' , 9 & & 9 % $ 7 6 3 & ' * 1 ' n & 0 0 8 ; n n n n & 3 0 0 0 ( & * o d v v & r q w u r o % o r f n % , 7 6 3 , f r q w u r o o h g 2 8 7 2 8 7 2 8 7 2 8 7 2 8 7 2 8 7 2 8 7 2 8 7 2 8 7 2 8 7 p q ( & ' 5 ( & 9 2 8 7 q ) & 3 0 & 3 3 & 3 0 & 3 3 9 6 [ 0 * + 6 + * / 6 / 3 : 0 + 0 ( & ) ' ' , 5 n n / 3 0 ) 6 2 6 3 , : l q g r z : d w f k g r j ! ) d l o 6 d i h : d w w % x o e : d w w % x o e 6 3 , d g m x v w d e o h 6 o h z 5 d w h a q ) a q ) a q ) q ) ! ! ! ! ) d l o 6 d i h & l u f x l w u \ ! n * $ 3 * & ) 7 p q p q p q p q p q p q p q p q p q p q p q block diagram and pin description l99dz80ep 8/68 doc id 18260 rev 5 table 2. pin definitions and functions pin symbol function 57, 58 gnd 1 ground: reference potential. gnd1 and gnd2 are internally connected. gnd1 supplies out1-3, gnd2 supplies out4-6 important: for the capability of driving the full current at the outputs, all pins of gnd must be externally connected! 17, 18, 26, 31, 32 gnd 2 17 sgnd signal ground: this pin is shared with gnd2 pin 2, 3, 45, 46, 51, 52 vs 1 power supply voltage for power stage outputs (external reverse protection required): for this input a ceramic capacitor as close as possible to gnd is recommended. vs1 supplies out1-3, out7-11 and the internal vs supply, vs2 supplies out4-6 important: for the capability of driving the full current at the outputs all pins of vs must be externally connected! 11, 12, 23, 36, 37 vs 2 48, 49, 50 out11 high-side-driver output 11: the output is built by a high-side switch and is intended for resistive loads, hence the internal reverse diode from gnd to the output is missing. for esd reason a diode to gnd is present but the energy which can be dissipated is limited. the high-side driver is a power dmos transistor with an internal parasitic reverse diode from the output to vs (bulk-drain-diode). the output is overcurrent and open load protected. important: for the capability of driving the full current at the outputs all pins of out11 must be externally connected! 59, 60 out1 half-bridge outputs 1,2,3,4,5,6: the output is built by a high side and a low side switch, which are internally connected. the output stage of both switches is a power dmos transistor. each driver has an internal parasitic reverse diode (bulk-drain-diode: high side driver from output to vs, low side driver from gnd to output). this output is over current and open load protected. 56 out2 55 out3 19, 20, 21, 22 out4 27, 28, 29, 30 out5 24, 25 out6 40 do serial data output: the diagnosis data is available via the spi and this 3-state-output. the output remains in 3-state, if the chip is not selected by the input csn (csn = high). 34 cm current monitor output: depending on the selected multiplexer bits of the control register this output sources an image of the instant current through the corresponding high side driver with a fixed ratio. 35 csn chip-select-not input: this input is low active and requires cmos logic levels. the serial data transfer between the device and the micro controller is enabled by pulling the input csn to low level. 41 di serial data input: the input requires cmos logic levels and receives serial data from the microcontroller. the data is a 24 bit control word and the most significant bit (msb, bit 23) is transferred first. 38 clk serial clock input: this input controls the internal shift register of the spi and requires cmos logic levels. 33 dir direction input: this input controls the h-bridge drivers l99dz80ep block diagram and pin description doc id 18260 rev 5 9/68 39 vcc supply voltage: 5 v supply. a ceramic capacitor as close as possible to gnd is recommended. 44 out9 high-side-driver output 9: the output is built by a high side switch and is intended for resistive loads; hence the internal reverse diode from gnd to the output is missing. for esd reason a diode to gnd is present but the energy which can be dissipated is limited. the high-side driver is a power dmos transistor with an internal parasitic reverse diode from the output to vs (bulk-drain-diode). the output is over current and open load protected. 42 pwmh pwmh input: this input signal can be used to control the h-bridge gate drivers 43 ecdr ecdr: using the device in ec control mode this pin is used to control the gate of an external mosfet. 62, 63 out7 high side driver output 8: see out9 important: this output can be configured to supply a bulb with low on- resistance or a led with higher on-resistance in a different application. 61 out8 47 out10/ec high-side-driver-output 10: see out9 important: beside the out10-hs on/off bit this output can be switched on setting the econ bit for electrochrome control mode with higher priority. 54 ecfd ecfd: using the device in ec control mode this pin is used as ?virtual gnd? for the ec-glass. for ec-glasses, that require a negative discharge voltage, this supplies the fast discharge voltage. if no ec-glass is used, this pin must be connected to ground. 53 ecv ecv: using the device in ec control mode this pin is used as voltage monitor input. for fast discharge an additional low-side-switch is implemented. 13 gh2 gh2: gate driver for power mos high side switch in half-bridge 2 14 sh2 sh2: source of high-side switch in half-bridge 2 15 gl2 gl2: gate driver for power mos low side switch in half-bridge 2 16 sl2 sl2: source of low side switch in half-bridge 2 64 gh1 gh1: gate driver for power mos high side switch in half-bridge 1 1 sh1 sh1: source of high-side switch in half-bridge 1 4 gl1 gl1: gate driver for power mos low side switch in half-bridge 1 5 sl1 sl1: source of low side switch in half-bridge 1 7 cp1p cp1p: charge pump pin for capacitor 1, positive side 8 cp1m cp1m: charge pump pin for capacitor 1, negative side 9 cp2p cp2p: charge pump pin for capacitor 2, positive side 10 cp2m cp2m: charge pump pin for capacitor 2, negative side 6 cp cp: charge pump output table 2. pin definitions and functions (continued) pin symbol function block diagram and pin description l99dz80ep 10/68 doc id 18260 rev 5 figure 2. pin connection (top view) & 3 3 & 3 0 & 3 3 & 3 0 & 3 & 0 ' , 5 & 6 1 9 6 9 6 * + 6 + * / 6 / * 1 ' 6 * 1 ' * 1 ' 2 8 7 2 8 7 2 8 7 2 8 7 9 6 2 8 7 2 8 7 * 1 ' 2 8 7 2 8 7 2 8 7 2 8 7 * 1 ' * 1 ' 2 8 7 9 6 9 6 2 8 7 ( & ' 5 3 : 0 + ' , ' 2 9 & & & / . 9 6 9 6 2 8 7 2 8 7 2 8 7 2 8 7 2 8 7 * 1 ' * 1 ' 9 6 2 8 7 2 8 7 ( & 9 ( & ) ' 9 6 2 8 7 2 8 7 2 8 7 7 4 ) 3 6 + 9 6 9 6 * + * / 6 / * $ 3 * & ) 7 l99dz80ep electrical specifications doc id 18260 rev 5 11/68 2 electrical specifications 2.1 absolute maximum ratings stressing the device above the rating listed in the ?absolute maximum ratings? table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality document. table 3. absolute maximum ratings symbol parameter/test condition value [dc voltage] unit v s1 , v s2 dc supply voltage -0.3 to +28 v single pulse / t max < 400 ms ?transient load dump? -0.3 to +40 v v cc stabilized supply voltage, logic supply -0.3 to v s +0.3 v v di, v clk , v csn , v do , v cm , v dir , v pwmh , v dir logic input / output voltage range -0.3 to v cc +0.3 v v outn, ecdr, ecv, ecfd output voltage (n = 1 to 11) -0.3 to v s +0.3 v v sl1 , v sh1 , v sl2 , v sh2 (v sxy ) high voltage signal pins -6 to 40 v v gl1 , v gh1 , v gl2 , v gh2 (v gxy ) high voltage signal pins v sxy -1 to v sxy +10; v cp +0.3 v v cp1p high voltage signal pins v s - 0.3 to v s +10 v v cp2p high voltage signal pins v s - 0.6 to v s +10 v v cp1m , v cp2m high voltage signal pins -0.3 to v s +0.3 v v cp high voltage signal pin v s1,2 26 v v s - 0.3 to v s +14 v v s1,2 > 26 v v s - 0.3 to +40 v i out2,3,9,10, ecv, ecfd output current (1) 1.25 a i out1,6,7 output current (1) (low on-resistance mode) 5 a i out7 output current (1) (high on-resistance mode) 5 a i out8 output current (1) 2.5 a i out4,5 output current (1) 10 a i out11 output current (1) 7.5 a i vs1cum maximum cumulated input current at vs 1 pins (1) 12.5 a i vs2cum maximum cumulated input current at vs 2 pins (1) 12.5 a i gnd1cum maximum cumulated output current at gnd 1 pins (1) 5 a i gnd2cum maximum cumulated output current at gnd 2 pins (1) 12.5 a 1. values for the absolute maximum dc current through the bond wires. this value does not consider maximum power dissipation or other limits. electrical specifications l99dz80ep 12/68 doc id 18260 rev 5 2.2 esd protection 2.3 thermal data table 4. esd protection parameter value unit all pins 2 (1) 1. hbm according to mil 883c, method 3015.7 or eia/jesd22-a114-a. kv power output pins: out1 ? out11, ecv, ecfd 4 (1) kv table 5. operating junction temperature symbol parameter value unit t j operating junction temperature -40 to 150 c table 6. temperature warning and thermal shutdown symbol parameter test condition min. typ. max. unit t jtw on temperature warning threshold (junction temperature) 130 150 c t jts on thermal shutdown threshold (junction temperature) 150 170 c t jtft thermal warning / shutdown filter time 32 s table 7. package thermal impedance symbol parameter value unit r thj-amb thermal resistance junction to ambient (max) see figure 5 k/w l99dz80ep electrical specifications doc id 18260 rev 5 13/68 2.4 package and pcb thermal data 2.4.1 tqfp-64 thermal data figure 3. tqfp-64 2 layer pcb figure 4. tqfp-64 4 layer pcb note: layout condition of r th and z th measurements (board finish thickness 1.6 mm +/- 10%, board double layer and four layers, board dimension 77 mm x114 mm, board material fr4, cu thickness 0.070mm (outer layers), cu thickness 0.035mm (inner layers), thermal vias separation 1.2 mm, thermal via diameter 0.3 mm +/- 0.08 mm, cu thickness on vias 0.025 mm, footprint dimension 6 mm x 6 mm). 4-layer pcb: cu on mid1 layer, cu on mid2 layer and cu on bottom layer: 62 cm 2 . z th measured on the major power dissipator contributor * $ 3 * & ) 7 * $ 3 * & ) 7 electrical specifications l99dz80ep 14/68 doc id 18260 rev 5 figure 5. tqfp-64 thermal impedance junction to ambient vs pcb copper area 7 l p h v = 7 + ? & : & x f p & x f p & x i r r w s u l q w / d \ h u * $ 3 * & ) 7 l99dz80ep electrical specifications doc id 18260 rev 5 15/68 2.5 electrical characteristics the voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 v v s 18 v, 4.75 v v cc 5.5 v; all outputs open; t j = -40 c to 150 c, unless otherwise specified. table 8. supply symbol parameter test condition min. typ. max. unit v s operating voltage range 5 28 v i vs(act) current consumption in active mode v s = 13.5 v (1) 1. this parameter is guaranteed by design 510ma i vs(stby) current consumption in standby mode v s =16v; v cc =5.3v; standby mode out1 - out11; ecv; ecdr floating t test = -40 c to 25 c 412a t test =85c (1) 625a v cc operating voltage range 4.5 5.5 v i vcc(active) v cc supply current v s =16v; v cc =5.3v; csn = v cc ; active mode out1 - out11; ecv; ecdr floating 510ma i vcc(stby) v cc standby current v s =16v; v cc =5.0v; csn = v cc ; active mode out1 - out11; ecv; ecfd ecdr floating t test = -40 c to 25 c 36a t test =85c (1) 48a v s =16v; v cc =5.3v; csn = v cc ; active mode out1 - out11; ecv; ecfd ecdr floating t test = -40 c to 125 c 25 a table 9. overvoltage and undervoltage detection symbol parameter test condition min. typ. max. unit v suv on vs uv threshold voltage (1) v s increasing 5.6 7.2 v v suv off vs uv threshold voltage (1) v s decreasing 5 5.9 v v suv hyst vs uv hysteresis (1) v suv on -v suv off 0.5 v t vsuvfilt vs uv filter time 48 s v sov off vs ov threshold voltage (1) v s increasing 18.5 24.5 v v sov on vs ov threshold voltage (1) v s decreasing 18.0 23.5 v v sov hyst vs ov hysteresis (1) v sov off -v sov on 1v electrical specifications l99dz80ep 16/68 doc id 18260 rev 5 t vsovfilt vs ov filter time 48 s v vccreshu upper v cc reset threshold (2) v cc increasing 5.8 7.5 v v vccreshd upper v cc reset threshold v cc decreasing 5.5 7.1 v v vccres hysth upper reset hysteresis v vccreshu - v vccreshd 0.1 v v poroff power-on-reset threshold v cc increasing 3.4 4.4 v v poron power-on-reset threshold v cc decreasing 3.1 4.1 v v por hystl power-on-reset hysteresis v poroffl - v poronl 0.3 v 1. vs = 5v to 28v 2. if v cc exceeds this value all registers ar e reset and the device enters standby mode. table 9. overvoltage and undervoltage detection (continued) symbol parameter test condition min. typ. max. unit table 10. current monitor output (cm) symbol parameter test condition min. typ. max. unit v cm functional voltage range 0 v cc -1v v i cm r current monitor output ratio: i cm /i out1,4,5,6,11 and 7 (low on- resistance) 0v v cm v cc -1v 1/10000 i cm /i out8 (low on-resistance) 1/6500 i cm /i out2,3,7,8,9,10 and 7,8 (high on- resistance) 1/2000 i cm acc current monitor accuracy acci cmout1,4,5,6,11 and 7(low on-res.) 0v v cm v cc -1v; i outmin =500ma; i out4,5max = 5.9 a; i out11max = 4.9 a; i out1,6max = 2.9 a; i out7max =1.4a 4% + 1%fs (1) 8% + 2%fs (1) acci cmout2,3,8,9,10 and 7(high on-res.) 0v v cm v cc -1v; i out.min =100ma; i out2,3,9,10max = 0.4a; i out7max = 0.3 a; i out8(low rdson)max = 0.6 a; i out8(high rdson)max =0.3a t cmb current monitor blanking time 32 s 1. fs (full scale) = i outmax *i cmr table 11. charge pump symbol parameter test condition min. typ. max. unit v cp charge pump output voltage v s =6v; i cp =-10ma v s +6 v s +7 v s +7.85 v v s 10 v; i cp =-15ma v s +11 v s +12 v s +13.5 v l99dz80ep electrical specifications doc id 18260 rev 5 17/68 2.6 outputs out1 - out11, ecv, ecfd the voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 v v s 18 v, 4.75 v v cc 5.5 v; all outputs open; t j = -40 c to 150 c, unless otherwise specified. i cp charge pump output current (1) v cp =v s +10v; v s = 13.5 v; c 1 =c 2 =c cp = 100 nf 25 47 ma i cplim charge pump output current limitation (2) v cp =v s ; v s = 13.5 v; c 1 =c 2 =c cp = 100 nf 29 70 ma v cp_low charge pump low threshold voltage v s +4.6 v s +5 v s +5.4 v t cp charge pump low filter time 64 s 1. i cp is the minimum current the device can provide to an external circuit without v cp going below v s +10v 2. i cplim is the maximum current, which flows out of the device in case of a short to v s table 11. charge pump (continued) symbol parameter test condition min. typ. max. unit table 12. on-resistance symbol parameter test condition min. typ. max. unit r on out1,6 on-resistance to supply or gnd v s =13.5v; t amb =+25c; i out1,6 =1.5a 300 400 m v s =13.5v; t amb =+125c; i out1,6 =1.5a 450 600 m r on out2,3 on-resistance to supply or gnd v s =13.5v; t amb =+25c; i out2,3 =0.4a 1600 2200 m v s =13.5v; t amb =+125c; i out2,3 =0.4a 2500 3400 m r on out4,5 on-resistance to supply or gnd v s =13.5v; t amb =+25c; i out4,5 =3.0a 150 200 m v s =13.5v; t amb =+125c; i out4,5 =3.0a 225 300 m r on out7 on-resistance to supply in low resistance mode v s =13.5v; t amb =+25c; i out7 =-0.8a 500 700 m v s =13.5v; t amb =+125c; i out7 =-0.8a 700 950 m on-resistance to supply in high resistance mode v s =13.5v; t amb =+25c; i out7 =-0.2a 1600 2400 m v s =13.5v; t amb =+125c; i out7 =-0.2a 2500 3400 m electrical specifications l99dz80ep 18/68 doc id 18260 rev 5 r on out8 on-resistance to supply in low resistance mode v s =13.5v; t amb =+25c; i out8 =-0.4a 800 1200 m v s =13.5v; t amb =+125c; i out8 =-0.4a 1200 1700 m on-resistance to supply in high resistance mode v s =13.5v; t amb =+25c; i out8 =-0.2a 1600 2400 m v s =13.5v; t amb =+125c; i out8 =-0.2a 2500 3400 m r on out9,10 on-resistance to supply v s =13.5v; t amb =+25c; i out9,10 =-0.4a 1600 2200 m v s =13.5v; t amb =+125c; i out9,10 =-0.4a 2500 3400 m r on out11 on-resistance to supply v s =13.5v; t amb =+25c; i out11 =-3.0a 100 140 m v s =13.5v; t amb =+125c; i out11 =-3.0a 140 190 m r on ecv,ecfd on-resistance to gnd v s =13.5v; t amb =+25c; i outecv,ecfd =+0.4a 1600 2200 m v s =13.5v; t amb =+125c; i outecv,ecfd =+0.4a 2500 3400 m i qlh switched-off output current high side drivers of out1- 6,9-11 v out = 0 v; standby mode -5 -2 a v out = 0 v; active mode -10.2 -7 a i qlh7,8 switched-off output current high side drivers of out7,8 v out = 0 v; standby mode -5 -2 a v out = 0 v; active mode -15 -10 a i qll switched-off output current low side drivers of out1-6 v out =v s ; standby mode 80 165 a v out =v s -0.5v; active mode -10 -7 a switched-off output current low side drivers of ecv v out =v s ; standby mode -15 15 a v out =v s -0.5v; active mode -10 -7 a switched-off output current low side drivers of ecfd v out = 4 v; standby mode 80 165 a v out = 4 v; active mode -10 10 a table 12. on-resistance (continued) symbol parameter test condition min. typ. max. unit l99dz80ep electrical specifications doc id 18260 rev 5 19/68 table 13. power outputs switching times symbol parameter test condition min. typ. max. unit t d on h output delay time high side driver on (all out except out 7,8 ) v s = 13.5 v; v cc =5v; corresponding low side driver is not active (1)(2)(3) 1. r load = 16 at out 1,6 and out 7,8 in low on-resistance mode 2. r load = 4 at out 4,5,11 3. r load = 64 at out 2,3,4,9,10 ecv, ecfd and out 7,8 in high on-resistance mode 10 40 80 s output delay time high side driver on (out 7,8 in high r dson mode) 15 35 60 s output delay time high side driver on (out 7,8 in low r dson mode) 10 35 80 s t d off h output delay time high side driver off (out 1,4,5,6,11 ) v s = 13.5 v; v cc =5v (1)(2)(3) 50 150 300 s output delay time high side driver off (out 2,3, 7,8,9,10 ) 40 70 100 s t d on l output delay time low side driver on v s = 13.5 v; v cc =5v; corresponding low side driver is not active (1)(2)(3) 15 30 70 s t d off l output delay time low side driver (out 1-6 ) off v s = 13.5 v; v cc =5v (1)(2)(3) 40 150 300 s output delay time low side driver (ecv, ecfd) off v s = 13.5 v; v cc =5v (1)(2)(3) 15 45 88 s t d hl cross current protection time (out 1-6 ) t cc onls_offhs ? t doffh (4) 4. t cc is the switch-on delay time if complement in half bridge has to switch off 40 200 400 s t d lh t cc onhs_offls ? t doffl (4) dv out /dt slew rate of outx, ecv, ecfd v s = 13.5 v; v cc =5v (1)(2)(3) 0.08 0.2 0.6 v/ s f pwmx(low) low pwm switching frequency v s = 13.5 v; v cc =5v 122 hz f pwmx(high) high pwm switching frequency v s = 13.5 v; v cc =5v 244 hz table 14. current monitoring symbol parameter test condition min. typ. max. unit |i oc1 |, |i oc6 | overcurrent threshold to supply or gnd v s =13.5v; v cc = 5 v; sink and source 35.3a |i oc2 |, |i oc3 |, |i ocecfd | 0.5 1.0 a |i oc4 |, |i oc5 | 69.2a electrical specifications l99dz80ep 20/68 doc id 18260 rev 5 |i oc7 | overcurrent threshold to supply in low on-resistance mode v s =13.5v; v cc =5v; source 1.5 2.5 a overcurrent threshold to supply in high on-resistance mode 0.35 0.65 a |i oc8 | overcurrent threshold to supply in low on-resistance mode 0.7 1.3 a overcurrent threshold to supply in high on-resistance mode 0.35 0.65 a |i oc9 |, |i oc10 | overcurrent threshold to supply 0.5 1.0 a |i oc11 |57.5a |i ocecv | output current limitation to gnd v s =13.5v; v cc =5v; sink 0.5 1.0 a t foc filter time of overcurrent signal duration of overcurrent condition to set the status bit 10 55 100 s f rec0 recovery frequency for oc; recovery frequency bit = 0 14khz f rec1 recovery frequency for oc; recovery frequency bit = 1 26khz |i old1 |, |i old6 | undercurrent threshold to supply or gnd v s =13.5v; v cc =5v; sink and source 83080ma |i old2 |, |i old3 |, |i oldecfd | 10 20 30 ma |i old4 |, |i old5 | 60 150 300 ma |i old7 | undercurrent threshold to supply in low on-resistance mode v s =13.5v; v cc =5v; source 15 40 60 ma undercurrent threshold to supply in high on-resistance mode 51015ma |i old8 | undercurrent threshold to supply in low on-resistance mode 10 30 45 ma undercurrent threshold to supply in high on-resistance mode 51015ma |i old9 |, |i old10 | undercurrent threshold to supply 10 20 30 ma |i old11 | 30 150 300 ma table 14. current monitoring (continued) symbol parameter test condition min. typ. max. unit l99dz80ep electrical specifications doc id 18260 rev 5 21/68 2.7 h-bridge driver |i oldecv | undercurrent threshold to gnd v s =13.5v; v cc =5v; sink 10 20 30 ma t fol filter time of open-load signal duration of open- load condition to set the status bit 0.5 2.0 3.0 ms table 14. current monitoring (continued) symbol parameter test condition min. typ. max. unit table 15. gate drivers for the external power-mos (h-bridge) symbol parameter test condition min. typ. max. unit drivers for external high-side power-mos i ghx(ch) average charge current (charge stage) t j =25c 0.3 a r ghx on-resistance (discharge- stage) v shx =0v; i ghx = 50 ma; t j =25c 468 v shx =0v; i ghx = 50 ma; t j =125c 810 v ghxh gate-on voltage outputs floating v shx + 8 v shx + 10 v shx + 11.5 v r gshx passive gate-clamp resistance v ghx =0.5v 15 k drivers for external low-side power-mos i glx(ch) average charge-current (charge stage) t j =25c 0.3 a r glx on-resistance (discharge- stage) v slx =0v; i ghx = 50 ma; t j =25c 468 v slx =0v; i ghx = 50 ma; t j =125c 810 v ghlx gate-on voltage outputs floating v slx + 8 v slx + 10 v slx + 11.5 v r gslx passive gate-clamp resistance 15 k table 16. gate drivers for the external power-mos switching times symbol parameter test condition min. typ. max. unit t g(hl)xhl propagation delay time high to low (switch mode) (1) v s =13.5v; v shx =0; r g =0 ; c g =2.7nf 1.5 s t g(hl)xlh propagation delay time low to high (switch mode) (1) v s =13.5v; v slx =0; r g =0 ; c g =2.7nf 1.5 s electrical specifications l99dz80ep 22/68 doc id 18260 rev 5 i ghxrmax maximum charge current (current mode) v s =13.5v; v shx =0; v ghx =1v; slew < 4:0 1f h 24.5 31 38.5 ma i ghxfmax maximum discharge current (current mode) v s =13.5v; v shx =0; v ghx =2v; slew < 4:0 1f h 18.5 25 33 ma di ighxr charge current accuracy v s =13.5v; v shx =0; v ghx =1v see figure 6 di ighxf discharge current accuracy v s =13.5v; v shx =0; v ghx =2v see figure 7 v dshxrsw switching voltage (v s -v sh ) between current mode and switch mode (rising) v s =13.5v 1.5 v v tdshxf (2) trigger voltage to sample the v gsh for switching between switch mode and current mode (falling) v s =13.5v; v ghx =4v 1.5 v v tgshxacc (2) sampled trigger voltage accuracy v s =13.5v; v shx =0 1 v t0 ghxr rise time (switch mode) v s =13.5v; v shx =0; r g =0 ; c g =2.7nf 45 ns t0 ghxf fall time (switch mode) v s =13.5v; v shx =0; r g =0 ; c g =2.7nf 85 ns t0 glxr rise time v s =13.5v; v slx =0; r g =0 ; c g =2.7nf 45 ns t0 glxf fall time v s =13.5v; v slx =0; r g =0 ; c g =2.7nf 85 ns t ccp programmable cross-current protection time 0.1 5 s f pwmh pwmh switching frequency (1) v s =13.5v; v slx =0; r g =0 ; c g = 2.7 nf; pwmh - duty cycle = 50 % 50 khz 1. without cross-current protection time t ccp 2. parameter not tested, typical value validated by characterization. table 16. gate drivers for the external power-mos switching times symbol parameter test condition min. typ. max. unit l99dz80ep electrical specifications doc id 18260 rev 5 23/68 figure 6. ighxr ranges figure 7. ighxf ranges * $ 3 * & ) 7 f x u u u h q w l q p $ g d w d l q s x w , * + [ u d f f x u d f \ , * + [ u 0 d [ , * + [ u 7 \ s , * + [ u 0 l q * $ 3 * & ) 7 f x u u h q w l q p $ g d w d l q s x w , * + [ i d f f x u d f \ , * + [ i 0 d [ , * + [ i 7 \ s , * + [ i 0 l q electrical specifications l99dz80ep 24/68 doc id 18260 rev 5 figure 8. h-driver delay times 9 * 6 + / [ w 9 & 6 1 3 : 0 + ' , 5 w w 9 & 6 1 3 : 0 + ' , 5 7 * + / [ / + 7 * + / [ + / * $ 3 * & ) 7 table 17. drain source monitoring symbol parameter test condition min. typ. max. unit v scd1 drain-source threshold voltage v s = 13.5 v 0.3 0.5 0.7 v v scd2 drain-source threshold voltage v s = 13.5 v 0.8 1 1.2 v v scd3 drain-source threshold voltage v s = 13.5 v 1.2 1.5 1.8 v v scd4 drain-source threshold voltage v s = 13.5 v 1.6 2 2.4 v t scd drain-source monitor filter time 3 5.5 8 s t scs drain-source comparator settling time v s = 13.5 v; v sh = jump from gnd to v s ? 5s l99dz80ep electrical specifications doc id 18260 rev 5 25/68 2.8 electrochrome mirror driver table 18. open-load monitoring symbol parameter test condition min. typ. max. unit v odsl low-side drain-source monitor low off-threshold voltage v slx =0v; v s = 13.5 v 0.14 * v s 0.18 * v s 0.21 * v s v v odsh low-side drain-source monitor high off-threshold voltage v slx =0v; v s = 13.5 v 0.75 * v s 0.85 * v s 0.95 * v s v v olshx output voltage of selected shx in open-load test mode v slx =0v; v s = 13.5 v 0.5 * v s v r pdol pull-down resistance of the non- selected shx pin in open-load mode v slx =0v; v s =13.5v; v shx =4.5v 20 k t ol open-load filter time 2 ms table 19. electrochrome mirror driver symbol parameter test condition min. typ. max. unit v ctrlmax maximum ec-control voltage bit0 = 1 control reg. 2 (1) 1.4 1.6 v bit0 = 0 control reg. 2 (1) 1.12 1.28 v dnl ecv (2) differential non linearity -1 1 lsb (3) idv ecv i voltage deviation between target and ecv dv ecv =v target (4) - v ecv ; ii ecdr i<1a -5 % - 1lsb (3) +5 % + 1lsb (3) mv dv ecvnr difference voltage between target and ecv sets flag if v ecv is below it dv ecv =v target (4) - v ecv ; toggle bitx = 1 status reg. x 120 mv dv ecvhi above it -120 mv t fecvnr ecv nr filter time 32 s t fecvhi ecv hi filter time 32 s v ecdrminhigh output voltage range i ecdr = -10 a 4.5 5.5 v v ecdrmaxlow i ecdr =10a 0 0.7 v i ecdr current into ecdr v target (4) >v ecv +500mv; v ecdr =3.5v -100 -10 a v target (4) l99dz80ep electrical specifications doc id 18260 rev 5 27/68 2.9 spi / logic ? electrical characteristics the voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6v v s 18 v, 4.75 v v cc 5.5 v; all outputs open; t j = -40 c to 150 c, unless otherwise specified. table 20. delay time from standby to active mode symbol parameter test condition min typ max unit t set delay time switching time from standby to active mode. time until output drivers are enabled after csn going to high and set bit 0 = 1 of control register 0. 250 310 410 s t wakup wake-up time switching from standby to active mode. time after the first falling edge of csn until the first positive clk edge, which latches en = 1 correctly into the device ?20s t awake stay awake time switching from standby to active mode. after the first rising edge of csn a second spi frame with en = 1 is correctly recognized ?256 s table 21. inputs: di, csn, clk, dir and pwmh symbol parameter test condition min typ max unit inputs: csn, clk, di, dir, pwmh v il input voltage low level v s =13.5v; v cc = 5.0 v 0.3 * v cc v v ih input voltage high level v s =13.5v; v cc =5.0v 0.7*v cc v v ihys input hysteresis v s =13.5v; v cc =5.0v 500 mv r csn in csn pull-up resistor v s =13.5v; v cc =5.0v; 0v v csn 0.7 * v cc 60 110 215 k r clk in clk pull-down resistor v s =13.5v; v cc =5.0v; 0.3 * v cc v clk v cc 60 110 215 k r di in di pull-down resistor v s =13.5v; v cc =5.0v; 0.3 * v cc v di v cc 60 110 215 k r dir dir pull-down resistor v s =13.5v; v cc =5.0v; 0.3 * v cc v dir v cc 60 110 215 k r pwmh pwmh pull-down resistor v s =13.5v; v cc =5.0v; 0.3 * v cc v pwmh v cc 60 110 215 k output: do v ol output voltage low level i ol =5ma; v s = 13.5 v; v cc =5.0v 0.3 * v cc v v oh output voltage high level i oh = -5 ma; v s =13.5v; v cc =5.0v 0.7 * v cc v i dolk 3-state leakage current v csn =v cc ; 0 < v do l99dz80ep electrical specifications doc id 18260 rev 5 29/68 figure 9. spi timing parameters t r in rise time of input signal di, clk, csn v s =13.5v; v cc = 5 v 100 ns t f in fall time of input signal di, clk, csn v s =13.5v; v cc = 5 v 100 ns table 23. dynamic characteristics (continued) symbol parameter test condition min. typ. max. unit * $ 3 * 0 6 & 6 1 ' 2 ' d w d r x w & / . ' d w d r x w ' d w d l q ' d w d l q ' , w 6 & / . w / & / . w + & / . w & / . 4 9 w & 6 1 4 7 w + & 6 1 w 6 ' , w 6 & 6 1 w & 6 1 4 9 electrical specifications l99dz80ep 30/68 doc id 18260 rev 5 figure 10. spi input and output timing parameters figure 11. spi delay description ' 2 o r z w r k l j k 9 & & w u ' 2 ' 2 k l j k w r o r z ' , & / . & 6 1 * $ 3 * 0 6 w i ' 2 9 & & 9 & & 9 & & 9 & & 9 & & w i l q w u l q 0 l f u r & r q w u r o o h u 0 d v w h u 6 o d y h 6 & . 0 , 6 2 * $ 3 * 0 6 w 6 & . u l v h w 6 & . i l o w w 6 & . 4 9 w v h w x s l99dz80ep electrical specifications doc id 18260 rev 5 31/68 figure 12. power-output (out<11:1>, ecv, ecfd) timing table 24. watchdog symbol parameter test condition min. typ. max. unit tc wdto watchdog time out 50 64 100 ms * $ 3 * 0 6 w u l q w & 6 1 b + , p l q w i l q & 6 1 w g 2 ) ) w 2 ) ) w g 2 1 w 2 1 2 x w s x w y r o w d j h r i d g u l y h u 2 x w s x w y r o w d j h r i d g u l y h u 2 1 v w d w h 2 ) ) v w d w h 2 1 v w d w h 2 ) ) v w d w h & 6 1 o r z w r k l j k g d w d i u r p v k l w u h j l v w h u l v w u d q v i h u u h g w r r x w s x w s r z h u v z l w f k h v application information l99dz80ep 32/68 doc id 18260 rev 5 3 application information 3.1 dual power supply: v s and v cc the power supply voltage v s supplies the power drivers and the power-mos gate drivers. for supplying the high-side drivers for the power- and gate-driver outputs, an internal charge-pump is used. the spi interface and the logic circuitry is supplied by v cc . due to the independent v cc supply the control and status information are not lost, if there are spikes or glitches on the power supply voltage. 3.2 wake up and active mode/standby mode after power up of v s and v cc the device operates in standby-mode. pulling the signal csn to low level wakes the device up and the analog part is activated (active mode). after at least 10 s, the first spi communication is valid and the en-bit can be used to set the en- mode. the device can be set into active mode writing a ?1? into the en-register. if the en-register is not set to ?1?, the device goes back to standby mode typical 256 s after the rising edge of csn and all latched data are cleared. in standby mode the current at v s (v cc ) is less than 6 a (5 a) for csn = high (do in 3-state). it is recommended to switch all outputs off before entering standby mode. 3.3 charge pump the charge pump uses two external capacitors, which are switched with a frequency of typically 125 khz. the output of the charge pump has a current limitation. in standby mode and after a thermal shutdown has been triggered the charge pump is disabled. if the charge pump output voltage remains too low for longer than t cp , the power-mos outputs, the ec- control are switched off and the h-bridge gate drivers are switched to resistive low. the cp_low bit has to be cleared through a software reset to reactivate the drivers. 3.4 diagnostic functions all diagnostic functions (overcurrent, open-load, power supply overvoltage /undervoltage, temperature warning and thermal shutdown) are internally filtered. the condition has to be valid for at least the associated filter time before the corresponding status bit in the status registers is set. the filters are used to improve the noise immunity of the device. the open- load and temperature warning functions are intended for information purpose and do not change the state of the output drivers. on contrary, the overcurrent condition disables the corresponding driver and thermal shutdown disables all drivers. without setting the overcurrent recovery bits in the input data register, the microcontroller has to clear the overcurrent status bits to reactivate the corresponding drivers. l99dz80ep application information doc id 18260 rev 5 33/68 3.5 overvoltage and undervoltage detection at v s if the power supply voltage v s rises above the overvoltage threshold v sov_off , the outputs out1 to out11, ecdr, ecv, ecfd are switched to high impedance state, the charge pump is disabled and the h-bridge gate drivers are switched into sink condition to protect the h-bridge and the load. when the voltage v s drops below the undervoltage threshold v suv_off (uv-switch-off voltage), the output stages are switched to high impedance to avoid the operation of the power devices without sufficient gate driving voltage (increased power dissipation). if the supply voltage v s recovers to normal operating voltage, the charge pump is switched on again, the cp_low bit is cleared and the output stages return to the programmed state. if the undervoltage/overvoltage recovery disable bit is set, the automatic turn-on of the drivers is deactivated. if the undervoltage/overvoltage recovery disable bit (ov_uv_rd) is set, the microcontroller needs to clear the status bits to reactivate the drivers. it is recommended to set ov_uv_rd bit to avoid a possible high current oscillation in case of a shorted output to gnd and low battery voltage. 3.6 overvoltage and undervoltage detection at v cc at power-on (v cc increases from undervoltage to v poroff ) the circuit is initialized by an internally generated power-on-reset (por). if the voltage v cc decreases below the low threshold (v poron ), the outputs are switched to 3-state (high impedance) and the status registers are cleared. if the voltage at pin v cc increases above the v cc reset high threshold v vccreshu , the device enters the reset state, all outputs are switched off and all internal registers are cleared. after the voltage at pin v cc has decreased below v vccreshl , the device enters normal operating mode again and the internal registers are reset. 3.7 temperature warning and shutdown if the junction temperature rises above the temperature warning threshold (t jtw ), a temperature warning flag is set after the temperature warning filter time (t jtft ) and can be read via spi. if the junction temperature increases above the temperature shutdown threshold (t jts ), the thermal shutdown bit is set and the power transistors of all output stages are switched off to protect the device after the thermal shutdown filter time. the gates of the h-bridge are discharged by the ?resistive low? mode. the temperature warning and thermal shutdown flags are latched and must be cleared by the microcontroller. this is done by a read and clear command on an arbitrary register, because both bits are part of the global status register. after these bits have been cleared, the output stages are reactivated. if the temperature is still above the thermal warning threshold, the thermal warning bit is set after t jtft . once this bit is set and the temperature is above the temperature shutdown threshold, temperature shutdown is detected after t jtft and the outputs are switched off. therefore the minimum time after which the outputs are switched off after the bits have been cleared in case the temperature is still above the thermo-shutdown threshold is twice the thermo-warning/- shutdown filter time t jtft . application information l99dz80ep 34/68 doc id 18260 rev 5 3.8 inductive loads each half bridge is built by internally connected high- and low-side power dmos transistors. due to the built-in reverse diodes of the output transistors, inductive loads can be driven at the outputs out1 to out6 without external freewheeling diodes. the high-side drivers out7 to out11 are intended to drive resistive loads. therefore only a limited energy (e < 1 mj) can be dissipated by the internal esd-diodes in freewheeling condition. for inductive loads (l > 100 h) an external freewheeling diode connected between gnd and the corresponding output is required. the low side driver at ecv does not have a freewheel diode built into the device. 3.9 open-load detection the open load detection monitors the load current in each activated output stage. if the load current is below the open load detection threshold for at least t fol the corresponding open- load bit is set in the status register. due to mechanical/electrical inertia of typical loads a short activation of the outputs (e.g. 3 ms) can be used to test the open load status without changing the mechanical/electrical state of the loads. 3.10 overcurrent detection in case of an overcurrent condition, a flag is set in the status register. if the overcurrent signal is valid for at least t foc , the overcurrent flag is set and the corresponding driver is switched off to reduce the power dissipation and to protect the integrated circuit. if the overcurrent recovery bit of the output is cleared, the microcontroller has to clear the status bits to reactivate the corresponding driver. 3.11 current monitor the current monitor output sources a current image at the current monitor output, which has three fixed ratios of the instantaneous current of the selected high-side driver. outputs with a resistance of 500 m and higher have a ratio of 1/2000, except for out8, which has a ratio of 1/6500, and those with a lower resistance one of 1/10000. the signal at output cm is blanked after switching on the driver until correct settlement of the circuitry. the bits cm_sel<3:0> define which of the outputs are multiplexed to the current monitor output cm. the current monitor output allows a more precise analysis of the actual state of the load rather than the detection of an open- or overload condition. for example, it can be used to detect the motor state (starting, free running, stalled). moreover, it is possible to control the power of the defroster more precisely by measuring the load current. the current monitor output is enabled after the current-monitor blanking time, when the selected output is switched on. if this output is off, the current monitor output is in high-impedance mode. 3.12 pwm mode of the power outputs each driver has a corresponding pwm enable bit, which can be programmed by the spi interface. if the pwm enable bit is set, the output is controlled by the logically and- combination of an internally generated pwm signal and the output control bit of the corresponding driver. the pwm-frequency of all outputs can be programmed to either 122 hz of 244 hz typically. the on-duty-cycle is set by the four 7-bit registers, which control l99dz80ep application information doc id 18260 rev 5 35/68 one pwm counter each. therefore the maximum on-time is 100% - 1 lsb. 1 lsb = 100/128 %. which output uses which corresponding pwm driver can be seen in the spi register definition. when programming a specific duty-cycle, the output on/off times as well as the slopes must be taken into account. 3.13 cross-current protection the six half-brides of the device are crosscurrent protected by an internal delay time. if one driver (ls or hs) is turned off, the activation of the other driver of the same half bridge is automatically delayed by the crosscurrent protection time. after the crosscurrent protection time is expired the slew-rate limited switch-off phase of the driver is changed to a fast turn- off phase and the opposite driver is turned-on with slew-rate limitation. due to this behavior, it is always guaranteed that the previously activated driver is completely turned off before the opposite driver starts to conduct 3.14 programmable soft-start function to drive loads with higher inrush current loads with start-up currents higher than the overcurrent limits (e.g. inrush current of lamps, start current of motors and cold resistance of heaters) can be driven by using the programmable softstart function (i.e. overcurrent recovery mode). each driver has a corresponding overcurrent recovery bit. if this bit is set, the device automatically switches the outputs on again after a programmable recovery time. the duty cycle in overcurrent condition can be programmed by the spi interface to about 12 % or 25 %. the pwm modulated current provides sufficient average current to power up the load (e.g. heat up the bulb) until the load reaches operating condition. the pwm frequency settles at 1.7 khz and 3 khz. the device itself cannot distinguish between a real overload and a non linear load like a light bulb. a real overload condition can only be qualified by time. for overload detection the microcontroller can switch on the light bulbs by setting the overcurrent recovery bit for the first e.g. 50 ms. after clearing the recovery bit the output is automatically switched off, if the overload condition remains. this overcurrent detection procedure has to be followed in order to make it possible to switch on the low side driver of a bridge output, if the associated high-side driver has been used in recovery mode before. application information l99dz80ep 36/68 doc id 18260 rev 5 figure 13. overcurrent recovery mode 3.15 h-bridge control (dir, pwmh, bits sd, sds) the pwmh input controls the drivers of the external h-bridge transistors. the motor direction can be chosen with the direction input (dir), the duty cycle and frequency with the pwmh input. with the spi-registers sd and sds four different slow-decay modes (via drivers and via diode) can be selected using the high side or the low side transistors. unconnected inputs are defined by internal pull-down current. w , / 2 $ ' 8 q o l p l w h g , q u x v k & x u u h q w / l p l w h g , q u x v k & x u u h q w l q s u r j u d p p d e o h u h f r y h u \ p r g h & x u u h q w / l p l w d w l r q * $ 3 * & ) 7 table 25. h-bridge control truth table n control pins control bits failure bits output pin comment dir pwmh hen sd sds cp_low ov uv ds tsd gh1 gl1 gh2 gl2 1 x x 0 x x x x x x x rl rl rl rl h-bridge disabled 2 x x 1 x x 1 0 0 0 0 rl rl rl rl charge pump voltage too low 3 x x 1 x x 0 x x x 1 rl rl rl rl thermo-shutdown 4x x 1xx 0 1000llllovervoltage 5x x 1 x x 0 001 0l (1) l (1) l (1) l (1) short-circuit (1) 6 0 1 1 x x 0 0 0 0 0 l h h l bridge h2/l1 on 7x 0 1 0 0 0 000 0 l h l h slow-decay mode ls1 and ls2 on 8 0 0 1 0 1 0 0 0 0 0 l h l l slow-decay mode ls1 on 9 1 0 1 0 1 0 0 0 0 0 l l l h slow-decay mode ls2 on l99dz80ep application information doc id 18260 rev 5 37/68 3.16 h-bridge driver slew-rate control the rising and falling slope of the drivers for the external high-side power-mos can be slew rate controlled. if this mode is enabled the gate of the external high-side power-mos is driven by a current source instead of a low-impedance output driver switch as long as the drain-source voltage over this power-mos is below the switch threshold. the current is programmed using the bits slew<4:0>, which represent a binary number. this number is multiplied by the minimum current step. this minimum current step is the maximum source- /sink-current (i ghxrmax / i ghxfmax ) divided by 31. programming slew<4:0> to 0 disables the slew rate control and the output is driven by the low-impedance output driver switch. 10 1 1 1 x x 0 0 0 0 0 h l l h bridge h1/l2 on 11 x 0 1 1 0 0 0 0 0 0 h l h l slow-decay mode hs1 and hs2 on 12 0 0 1 1 1 0 0 0 0 0 l l h l slow-decay mode hs2 on 13 1 0 1 1 1 0 0 0 0 0 h l l l slow-decay mode hs1 on 1. only the half-bridge (low and high-side), in which one mosfet is in short circuit condition is switched off. both mosfets of the other half-bridge remain active and driven by dir and pwmh table 25. h-bridge control truth table (continued) n control pins control bits failure bits output pin comment dir pwmh hen sd sds cp_low ov uv ds tsd gh1 gl1 gh2 gl2 application information l99dz80ep 38/68 doc id 18260 rev 5 figure 14. h-bridge gshx slope 3.17 resistive low the resistive output mode protects the l99dz80ep and the h-bridge in the standby mode and in some failure modes (thermal shut down (tsd), charge pump low (cp_low) and stuck-at-?1? at pin di). when a gate driver changes into the resistive output mode due to a failure a sequence is started. in this sequence the concerning driver is switched into sink condition for 32 s to 64 s to ensure a fast switch-off of the h-bridge transistor. if slew rate control is enabled, the sink condition is slew-rate controlled. afterwards the driver is switched into the resistive output mode (resistive path to source). 3.18 short circuit detection/drain source monitoring the drain source voltage of each activated external mosfet of the h-bridge is monitored by comparators to detect shorts to ground or battery. if the voltage-drop over the external mosfet exceeds the threshold voltage v scd for longer than the short current detection time t scd the corresponding gate driver switches the external mosfet off and the corresponding drain source monitoring flag (ds_mon[3:0]) is set. the ds_mon bits have 9 * 6 + [ w & x u u h q w & r q w u r o o h g & x u u h q w & r q w u r o o h g / r z 5 h v l v w l y h 6 z l w f k & r q w u r o o h g 9 ' 6 + [ w * $ 3 * & ) 7 l99dz80ep application information doc id 18260 rev 5 39/68 to be cleared through the spi to reactivate the gate drivers. the drain source monitoring has a filter time of typ. 6 s. this monitoring is only active while the corresponding gate driver is activated. if a drain-source monitor event is detected, the corresponding gate-driver remains activated for at maximum the filter time. when the gate driver switches on, the drain-source comparator requires the specified settling time until the drain-source monitoring is valid. during this time, this drain-source monitor event may start the filter time. the threshold voltage v scd can be programmed using the spi. figure 15. h-bridge diagnosis 3.19 h-bridge monitoring in off-mode the drain source voltages of the h-bridge driver external transistors can be monitored, while the transistors are switched off. if either bit ol_h1l2 or ol_h2l1 is set to ?1?, while bit hen = ?1?, the h-drivers enter resistive low mode and the drain-source voltages can be monitored. since the pull-up resistance is equal to the pull-down resistance on both sides of table 26. h-bridge ds-monitor threshold diag<1> diag<0> monitoring threshold voltage (typical) 00 v scd1 =0.5v 01 v scd2 =1.0v 10 v scd3 =1.5v 11 v scd4 =2.0v 0 9 v * + 9 6 6 + * / 6 / 9 6 * + 6 + * / 6 / n n * d w h ' u l y h u + 6 * d w h ' u l y h u / 6 ' 6 0 r q l w r u l q j + 6 ' 6 0 r q l w r u l q j / 6 2 / 0 r q l w r u l q j 9 7 k u h v 9 7 k u h v n n * d w h ' u l y h u + 6 * d w h ' u l y h u / 6 ' 6 0 r q l w r u l q j + 6 ' 6 0 r q l w r u l q j / 6 2 / 0 r q l w r u l q j 9 7 k u h v 9 7 k u h v * $ 3 * & ) 7 application information l99dz80ep 40/68 doc id 18260 rev 5 the bridge a voltage of 2/3 v s on the pull-up high-side and 1/3 v s on the low side is expected, if they drive a low-resistive inductive load (e.g. motor). if the drain source voltage on each of these power-mos is less than 1/6 v s , the drain-source monitor bit of the associated driver is set. in case of a short to ground the drain-source monitor bits of both low-side gate drivers are set. a short to v s can be diagnosed by setting the ?h-bridge ol high threshold (h-olth high)? bit to one. figure 16. h-bridge open-load detection (no open-load detected) figure 17. h-bridge open-load detection (open-load detected) 0 p n n n 9 v 9 v 9 7 9 v ' 6 0 ' 6 0 9 7 9 v 9 v * $ 3 * & ) 7 0 p n n n 2 s h q 9 v 9 7 9 v ' 6 0 ' 6 0 9 7 9 v 9 v * $ 3 * & ) 7 l99dz80ep application information doc id 18260 rev 5 41/68 figure 18. h-bridge open-load detection (short to ground detected) figure 19. h-bridge open-load detection with h-olth high = ?1? (short to v s detected) 3.20 programmable cross current protection both external mosfet transistors in one half-bridge are disabled for the cross-current protection time (t ccp ) after one mosfet inside this halfbridge is switched off to prevent current flowing from the high-side to the low-side mosfet. the cross current protection time t ccp can be programmed by spi using bits copt<3:0>. 0 p n n n * 1 ' 9 7 9 v ' 6 0 ' 6 0 9 7 9 v * 1 ' 6 k r u w 9 v * $ 3 * & ) 7 0 p n n n ' 6 0 ' 6 0 9 7 9 v 6 k r u w 9 v 9 v 9 v 9 7 9 v * $ 3 * & ) 7 application information l99dz80ep 42/68 doc id 18260 rev 5 3.21 controller of electrochromic glass the voltage of an electrochromic element connected at pin ecv can be controlled to a target value, which is set by the bits ec<5:0>. setting bit econ enables this function. an on-chip differential amplifier and an external mos source follower, with its gate connected to pin ecdr, and which drives the electrochrome mirror voltage at pin ecv, form the control loop. the drain of the external mos transistor is supplied by out10. a diode from pin ecv (anode) to pin ecdr (cathode) has been placed on the chip to prot ect the external mos source follower. a capacitor of at least 5 nf has to be added to pin ecdr for loop-stability. the target voltage is binary coded with a full-scale range of 1.5 v. if bit ec_hv s set to '0', the maximum controller output voltage is clamped to 1.2 v without changing the resolution of bits ec<5:0>. when programming the ecvls driver to on-state, the voltage at pin ecv is pulled to ground by a 1.6 low-side switch until the voltage at pin ecv is less than dv ecvhi higher than the target voltage (fast discharge). the status of the voltage control loop is reported via spi. bit ecv_vhi is set, if the voltage at pin ecv is higher, whereas bit ecv_vnr in the same status register is set, if the voltage at pin ecv is lower than the target value. both status bits are valid, if they are stable for at least the ecv hi /ecv nr ? filter time and are not latched. since out10 is the output of a high-side driver, it contains the same diagnose functions as the other high-side drivers (e.g. during an overcurrent detection, the control loop is switched off). in electrochrome mode, out10 cannot be controlled by pwm mode. for ems reasons, the loop capacitor at pin ecdr as well as the capacitor between ecv and gnd have to be placed to the respective pins as close as possible (see figure 20 for details). table 27. cross-current protection time copt<3> copt<2> copt<1> copt<0> min typ max unit 0 0 0 0 150 250 360 ns 0 0 0 1 390 500 670 ns 0 0 1 0 590 750 980 ns 0 0 1 1 800 1000 1280 ns 0 1 0 0 1000 1250 1600 ns 0 1 0 1 1210 1500 1910 ns 0 1 1 0 1420 1750 2220 ns 0 1 1 1 1630 2000 2540 ns 1 0 0 0 1830 2250 2850 ns 1 0 0 1 2050 2500 3120 ns 1 0 1 0 2250 2750 3450 ns 1 0 1 1 2460 3000 3760 ns 1 1 0 0 2660 3250 4100 ns 1 1 0 1 2880 3500 4370 ns 1 1 1 0 3080 3750 4680 ns 1 1 1 1 3200 4000 5000 ns l99dz80ep application information doc id 18260 rev 5 43/68 if the electrochrome element is connected between the pins ecv and ecfd instead between ecv and ground, a negative voltage can be applied to the device by pulling ecfd to a higher value than ecv, which is connected to ground by a 1.6 low-side switch. in this mode the voltage at pin ecfd is controlled to the target value defined by the register ec<5:0>. this is done using an on-chip source-follower transistor (see figure 21 for details). the negative discharge is enabled by setting bit ecnd to ?1?. when programming the ecfdls driver to on-state, the voltage at pin ecfd is pulled to ground by a 1.6 low-side switch until the voltage at pin ecfd is less than dv ecfdhi higher than the target voltage (fast discharge). during normal (positive) voltage control the low side driver at pin ecfd must be switched on to connect the electrochrome element to ground. pin ecdr is pulled resistively (r ecdrdis ) to ground while not in electrochrome mode. figure 20. electrochrome mirror driver with mirror referenced to ground * 1 ' 6 3 , ' u r s 5 h j x o d w r u ( & ' 5 2 8 7 ( & 9 9 6 f r p s d w l e o h ( & 0 l u u r u q ) ? ) d v w ( & * o d v % u l j k w h q l q j 3 ( & ) ' $ o o f r p s r q h q w v p x v w e h s o d f h g f o r v h w r j h w k h u d q g f r q q h f w h g z l w k d y h u \ o r z l p s h g d q f h q ) / r j l f ' $ & 9 6 9 r o w d j h q r w u h d f k h g 9 r o w d j h w r r k l j k 9 6 f r p s d w l e o h ) d v w ' l v f k d u j h % l w u h v r o x w l r q q q ( & 9 r o w d j h & r q w u r o ) d v w ' l v f k d u j h q q 9 6 f r p s d w l e o h * $ 3 * & ) 7 application information l99dz80ep 44/68 doc id 18260 rev 5 figure 21. electrochrome mirror driver with mirror referenced to ecfd for negative discharge 3.22 watchdog the watchdog monitors the c during normal operation within a nominal trigger cycle of 60ms. the watchdog is triggered by toggling the watchdog bit, which restarts the watchdog timer (i.e. content of the watchdog trigger bit has to be inverted). if no watchdog bit inversion has been occurred during the watchdog time-out time t wdto the h-bridge drivers switch into resistive-low condition, all power outputs are switched off, the electrochrome driver is disabled and the device enters standby mode. * 1 ' 6 3 , ' u r s 5 h j x o d w r u ( & ' 5 2 8 7 ( & 9 ( & 0 l u u r u n q ? ) d v w ( & * o d v % u l j k w h q l q j 3 ( & ) ' q q ) q ) $ o o f r p s r q h q w v p x v w e h s o d f h g f o r v h w r j h w k h u d q g f r q q h f w h g z l w k d y h u \ o r z l p s h g d q f h / r j l f ' $ & 9 6 9 r o w d j h q r w u h d f k h g 9 r o w d j h w r r k l j k 9 6 f r p s d w l e o h ) d v w ' l v f k d u j h % l w u h v r o x w l r q q q ( & 9 r o w d j h & r q w u r o ) d v w ' l v f k d u j h q q 9 6 f r p s d w l e o h * $ 3 * & ) 7 l99dz80ep functional description of the spi doc id 18260 rev 5 45/68 4 functional description of the spi 4.1 general description the spi complies with standard st-spi interface version 3.1. its communication is based on a serial peripheral interface structure using csn (chip select not), di (serial data in), do (serial data out/error) and clk (serial clock) signal lines. 4.1.1 chip select not (csn) the csn input pin is used to select the serial interface of this device. when csn is high, the output pin (do) is in high impedance state. a low signal wakes up the device and a serial communication can be started. the state when csn is going low until the rising edge of csn is called a communication frame. 4.1.2 serial data in (di) the di input pin is used to transfer data serially into the device. the data applied to the di is sampled at the rising edge of the clk signal. a stuck-at ?0? or ?1? enters the standby mode. 4.1.3 serial clock (clk) the clk input signal provides the timing of the serial interface. the data input (di) is latched at the rising edge of serial clock clk. the spi can be driven by a micro controller with its spi peripheral running in following mode: cpol = 0 and cpha = 0. data on serial data out (do) is shifted out at the falling edge of the serial clock (clk). the serial clock clk must be active only during a frame (csn low). any other switching of clk close to any csn edge could generate set up/hold violations in the spi logic of the device. the clock monitor counts the number of clock pulses during a communication frame (while csn is low). if the number of clk pulses does not correspond to the frame width indicated in the functional description of the spi l99dz80ep 46/68 doc id 18260 rev 5 this 8-bit register indicates the spi frame length (24 bit) and the availability of additional features. each communication frame consists of a command byte, which is followed by two data bytes. the data returned on do within the same frame always starts with the l99dz80ep functional description of the spi doc id 18260 rev 5 47/68 4.2 command byte ocx: operation code ax: address dx: data bit each communication frame starts with a command byte. it consists of an operating code which specifies the type of operation ( functional description of the spi l99dz80ep 48/68 doc id 18260 rev 5 03h control register 3 read/write high-side recovery mode, pwm setup and current- monitor selection 04h control register 4 read/write h-bridge driver control 05h control register 5 read/write pwm register 06h control register 6 read/write pwm register 10h status register 0 read/clear output bridge overcurrent and h-bridge drain-source diagnosis 11h status register 1 read/clear output bridge and h-bridge open-load diagnosis 12h status register 2 read/clear high-side overcurrent/open-load and electrochrome diagnosis 13h status register 3 read/clear v s and chargepump diagnosis 3fh configuration reg. read/write mask bits in global status register table 31. rom memory map address name access content 00h id header read only 4300h (assp st_spi) 01h version read only 0300h 02h product code 1 read only 5200h (82 st_spi) 03h product code 2 read only 4800h (h st_spi) 3eh spi-frame id. read only 4200h spi-frame-id (st_spi) table 30. ram memory map (continued) address name access content l99dz80ep spi - control and status registers doc id 18260 rev 5 49/68 5 spi - control and status registers table 32. global status byte bit76543 210 name gl_er co_er c_reset tsd tw uov_oc_ds ol nr reset00100 000 gl_er: global error flag. failures of bits 6 to 0 are always linked to the global error flag. this flag is set, if at least one of these bits indicates a failure. it is reflected via the do pin while csn is held low and no spi clock signal is applied. this operation does not cause the communication error bit in the spi - control and status registers l99dz80ep 50/68 doc id 18260 rev 5 5.1 control register 0 5.2 control register 1 table 33. control register 0 bit name access reset content 15 out1_hs on/off read/write 0 the corresponding output driver is activated, if this bit is set. setting the pwm enable bit, the driver is only switched on, if the pwm timer enables it. an internal cross-current protection prevents, that both the low- and high-side of the half-bridges out1-out6 are switched on simultaneously. 14 out1_ls on/off read/write 0 13 out2_hs on/off read/write 0 12 out2_ls on/off read/write 0 11 out3_hs on/off read/write 0 10 out3_ls on/off read/write 0 9 out4_hs on/off read/write 0 8 out4_ls on/off read/write 0 7 out5_hs on/off read/write 0 6 out5_ls on/off read/write 0 5 out6_hs on/off read/write 0 4 out6_ls on/off read/write 0 30 0 reserved (must be set to ?0?) 20 0 10 0 0 en read/write 0 the device is switched into active mode, if en is ?1?. it enters the standby mode, if the en bit is ?0?. in standby mode all bits are reset. table 34. control register 1 bit name access reset content 15 out7_hs1 on/off read/write 0 14 out7_hs2 on/off read/write 0 13 out8_hs1 on/off read/write 0 12 out8_hs2 on/off read/write 0 11 out9_hs on/off read/write 0 the corresponding output driver is activated, if this bit is set. setting the pwm enable bit, the driver is only switched on, if the pwm timer enables it. 10 out10_hs on/off read/write 0 9 out11_hs on/off read/write 0 8 ecv_ls on/off read/write 0 hs1 hs2 mode 00 off 0 1 low on-resistance 1 0 high on-resistance 11 off l99dz80ep spi - control and status registers doc id 18260 rev 5 51/68 5.3 control register 2 7 ec<5> read/write 0 the reference voltage for the electrochrome voltage controller at pins ecv and ecfd is binary coded. 6 ec<4> read/write 0 5 ec<3> read/write 0 4 ec<2> read/write 0 3 ec<1> read/write 0 2 ec<0> read/write 0 1 econ read/write 0 the electrochrome control is activated by setting this bit to ?1?. this enables the driver at pin ecdr and switches out10 directly on ignoring bit out10_hs on/off. 0 ecfd_ls on/off read/write 0 the corresponding output driver is activated, if this bit is set. setting the pwm enable bit, the driver is only switched on, if the pwm timer enables it. table 34. control register 1 (continued) bit name access reset content table 35. control register 2 bit name access reset content 15 out1_ocr read/write 0 setting this bit to high enables the overcurrent recovery mode for the corresponding output. 14 out2_ocr read/write 0 13 out3_ocr read/write 0 12 out4_ocr read/write 0 11 out5_ocr read/write 0 10 out6_ocr read/write 0 9 ecv_ocr read/write 0 8 ecnd read/write 0 setting this bit to ?1? puts the electrochrome controller into the negative discharge mode. 7 out1_pwm3 read/write 0 setting this bit to ?1? enables the pwm mode for the corresponding output. 6 out2_pwm1 read/write 0 5 out3_pwm2 read/write 0 4 out4_pwm1 read/write 0 3 out5_pwm2 read/write 0 2 out6_pwm3 read/write 0 1 ecv_pwm4 read/write 0 0 ecv_hv read/write 0 setting this bit to ?1? sets the maximum electrochrome controller voltage to 1.5 v (typ.). a ?0? clamps it to 1.2v (typ.). spi - control and status registers l99dz80ep 52/68 doc id 18260 rev 5 5.4 control register 3 table 36. control register 3 bit name access reset content 15 out7_ocr read/write 0 setting this bit to high enables the overcurrent recovery mode for the corresponding output. 14 out8_ocr read/write 0 13 out9_ocr read/write 0 12 out10_ocr read/write 0 11 out11_ocr read/write 0 10 out7_pwm1 read/write 0 setting this bit to ?1? enables the pwm mode for the corresponding output. 9 out8_pwm2 read/write 0 8 out9_pwm3 read/write 0 7 out10_pwm4 read/write 0 6 out11_pwm4 read/write 0 5 ocr_freq read/write 0 this bit defines the overcurrent recovery frequency (0: 1.7khz (typ.) 1: 3khz (typ.)) 4 ov_uv_rd read/write 0 if this bit is set, the associated status bit has to be cleared after an overvoltage /undervoltage event to enable the output drivers again. 3 cm_sel<3> read/write 0 a current image of the selected binary coded output is multiplexed to the cm output. if a corresponding output does not exist, the current monitor is deactivated (especially ?0000?). 2 cm_sel<2> read/write 0 1 cm_sel<1> read/write 0 0 cm_sel<0> read/write 0 cm_sel<3:0> selected output 0000 3-state 0001 out<1> 0010 out<2> 0011 out<3> 0100 out<4> 0101 out<5> 0110 out<6> 0111 out<7> 1000 out<8> 1001 out<9> 1010 out<10> 1011 out<11> 1100 reserved 1101-1111 3-state l99dz80ep spi - control and status registers doc id 18260 rev 5 53/68 5.5 control register 4 5.6 control register 5 table 37. control register 4 bit name access reset content 15 slew<4> read/write 0 binary coded slew rate current of the h-bridge 14 slew<3> read/write 0 13 slew<2> read/write 0 12 slew<1> read/write 0 11 slew<0> read/write 0 10 h-olth high read/write 0 h-bridge ol high threshold (5/6 * v s ) select 9 ol_h1l2 read/write 0 test open-load condition between h1 and l2 8 ol_h2l1 read/write 0 test open-load condition between h2 and l1 7 sd read/write 0 slow decay 6 sds read/write 0 slow decay single 5 copt<3> read/write 1 cross-current protection time (default 4000ns) 4 copt<2> read/write 1 3 copt<1> read/write 1 2 copt<0> read/write 1 1 diag<1> read/write 0 drain-source monitoring threshold voltage 0 diag<0> read/write 0 table 38. control register 5 bit name access reset content 15 0 0 reserved (must be set to ?0?) 14 pwm2<6> read/write 0 binary coded pwm2 on-duty-cycle 13 pwm2<5> read/write 0 12 pwm2<4> read/write 0 11 pwm2<3> read/write 0 10 pwm2<2> read/write 0 9 pwm2<1> read/write 0 8 pwm2<0> read/write 0 7 pwmfreq read/write 0 pwm-frequency (0: 122 hz or 1: 244 hz) spi - control and status registers l99dz80ep 54/68 doc id 18260 rev 5 5.7 control register 6 6 pwm1<6> read/write 0 binary coded pwm1 on-duty-cycle 5 pwm1<5> read/write 0 4 pwm1<4> read/write 0 3 pwm1<3> read/write 0 2 pwm1<2> read/write 0 1 pwm1<1> read/write 0 0 pwm1<0> read/write 0 table 38. control register 5 (continued) bit name access reset content table 39. control register 6 bit name access reset content 15 0 0 reserved (must be set to ?0?) 14 pwm4<6> read/write 0 binary coded pwm4 on-duty-cycle 13 pwm4<5> read/write 0 12 pwm4<4> read/write 0 11 pwm4<3> read/write 0 10 pwm4<2> read/write 0 9 pwm4<1> read/write 0 8 pwm4<0> read/write 0 7 0 0 reserved (must be set to ?0?) 6 pwm3<6> read/write 0 binary coded pwm3 on-duty-cycle 5 pwm3<5> read/write 0 4 pwm3<4> read/write 0 3 pwm3<3> read/write 0 2 pwm3<2> read/write 0 1 pwm3<1> read/write 0 0 pwm3<0> read/write 0 l99dz80ep spi - control and status registers doc id 18260 rev 5 55/68 5.8 configuration register 5.9 status register 0 table 40. configuration register bit name access reset content 15 0 0 reserved (must be set to ?0?) 14 0 0 13 0 0 12 0 0 11 0 0 10 0 0 90 0 80 0 70 0 6 hen read/write 0 a ?1? enables the h-bridge 5 mask ol hs1 read/write 0 masks open-load of high-side 1 to global status register 4 mask ol ls1 read/write 0 masks open-load of low-side 1 to global status register 3 mask tw read/write 0 masks thermo warning to global status register 2 mask ec ol read/write 0 masks open-load of ecv, ecfdhs, ecfdls and out10 1 mask ol read/write 0 masks all open-load diagnosis to global status register 0 wd read/write 0 watchdog table 41. status register 0 bit name access content 15 out1_hs oc read/clear overcurrent status bit of the corresponding output driver. a ?1? indicates that an overcurrent has occurred. 14 out1_ls oc read/clear 13 out2_hs oc read/clear 12 out2_ls oc read/clear 11 out3_hs oc read/clear 10 out3_ls oc read/clear 9 out4_hs oc read/clear 8 out4_ls oc read/clear 7 out5_hs oc read/clear 6 out5_ls oc read/clear 5 out6_hs oc read/clear 4 out6_ls oc read/clear spi - control and status registers l99dz80ep 56/68 doc id 18260 rev 5 5.10 status register 1 3 ds_mon_hs<2> read/clear ds-monitoring bit. a ?1? indicates that a drain-monitoring event (short- circuit or open-load) has occurred. 2 ds_mon_hs<1> read/clear 1 ds_mon_ls<2> read/clear 0 ds_mon_ls<1> read/clear table 41. status register 0 (continued) bit name access content table 42. status register 1 bit name access content 15 out1_hs ol read/clear open-load status bit of the corresponding output driver. a ?1? indicates that an open-load event has occurred. 14 out1_ls ol read/clear 13 out2_hs ol read/clear 12 out2_ls ol read/clear 11 out3_hs ol read/clear 10 out3_ls ol read/clear 9 out4_hs ol read/clear 8 out4_ls ol read/clear 7 out5_hs_ol read/clear 6 out5_ls ol read/clear 5 out6_hs ol read/clear 4 out6_ls ol read/clear 30 read reserved 20 read 10 read 00 read l99dz80ep spi - control and status registers doc id 18260 rev 5 57/68 5.11 status register 2 5.12 status register 3 table 43. status register 2 bit name access content 15 out7 oc read/clear overcurrent and open-load status bit of the corresponding output driver 14 out7 ol read/clear 13 out8 oc read/clear 12 out8 ol read/clear 11 out9 oc read/clear 10 out9 ol read/clear 9 out10 oc read/clear 8 out10 ol read/clear 7 out11 oc read/clear 6 out11 ol read/clear 5 ecv oc read/clear 4 ecv ol read/clear 3 vs uv read/clear v s undervoltage and overvoltage status bit. 2 vs ov read/clear 1 ecv_vnr read/clear electrochrome voltage not reached / too high status bits 0 ecv_vhi read/clear table 44. status register 3 bit name access content 15 0 read reserved 14 0 read 13 0 read 12 0 read 11 0 read 10 0 read 9 0 read 8 0 read 7 0 read 6 0 read spi - control and status registers l99dz80ep 58/68 doc id 18260 rev 5 5 ecfdh oc read/clear overcurrent and open-load status bit of the corresponding output driver 4 ecfdh ol read/clear 3 ecfd oc read/clear 2 ecfd ol read/clear 1 0 read reserved 0 cp low read/clear this bit indicates, that the charge pump voltage is too low table 44. status register 3 (continued) bit name access content l99dz80ep package and packing information doc id 18260 rev 5 59/68 6 package and packing information 6.1 ecopack ? package in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. 6.2 tqfp-64 mechanical data table 45. tqfp-64 mechanical data symbol millimeters min. typ. max. a 1,20 a1 0,05 0,15 a2 0,95 1,00 1,05 b 0,17 0,22 0,27 c 0,09 0,20 d 11,80 12,00 12,20 d1 9,80 10,00 10,20 d2 (1) 1. the size of exposed pads is variable depending on lead frame design and pad size end user should verify "d2" and "e2" dimensions for each device application 5,85 6,00 6,15 d3 7,50 e 11,80 12,00 12,20 e1 9,80 10,00 10,20 e2 (1) 5,85 6,00 6,15 e3 7,50 e 0,50 l 0,45 0,60 0,75 l1 1,00 k 0 3,50 7 ccc 0,08 package and packing information l99dz80ep 60/68 doc id 18260 rev 5 figure 23. tqfp-64 package dimension * $ 3 * & ) 7 l99dz80ep package and packing information doc id 18260 rev 5 61/68 6.3 tqfp-64 packing information the devices can be packed in tray or tape and reel shipments (see the figure 1: device summary on page 1 for packaging quantities). figure 24. tqfp-64 power lead-less tray shipment (no suffix) (part 1) * $ 3 * & ) 7 package and packing information l99dz80ep 62/68 doc id 18260 rev 5 figure 25. tqfp-64 power lead-less tray shipment (no suffix) (part 2) * $ 3 * & ) 7 l99dz80ep package and packing information doc id 18260 rev 5 63/68 figure 26. tqfp-64 power lead-less tape and reel shipment (suffix ?tr?) (part 1) * $ 3 * & ) 7 $ % . ) 3 : package and packing information l99dz80ep 64/68 doc id 18260 rev 5 figure 27. tqfp-64 power lead-less tape and reel shipment (suffix ?tr?) (part 2) ' l p h q v l r q o l v w $ q q r w h $ $ $ % % % ' ' . . 0 l o l p h w h u $ q q r w h . 3 3 3 3 ( ) 7 : 0 l o l p h w h u * $ 3 * & ) 7 l99dz80ep revision history doc id 18260 rev 5 65/68 7 revision history table 46. document revision history date revision change 20-dec-2010 1 initial release 10-mar-2011 2 updated features list. updated following tables: ? table 1: device summary ? table 2: pin definitions and functions : gh2, sh2, gl2, sl2: updated functions ? table 7: package thermal impedance ? table 8: supply : i vcc(stby) : set max value to tbd ? table 13: power outputs switching times : t d hl , t d lh : updated parameter ? table 31: rom memory map : updated content for address 01h ? table 40: configuration register : bit 5, 4, 3 and 1: updated contents updated following sections: ? section 3.5: overvoltage and undervoltage detection at vs ? section 3.19: h-bridge monitoring in off-mode ? section 3.20: programmable cross current protection updated figure 21: electrochrome mirror driver with mirror referenced to ecfd for negative discharge added section 6.3: tqfp-64 packing information revision history l99dz80ep 66/68 doc id 18260 rev 5 06-apr-2011 3 table 8: supply : ?i vcc(stby) : changed tbd at 6 a and updated v cc from 5.1 v t0 5.0 v; added test condition for v cc = 5.3 v table 9: overvoltage and undervoltage detection : ?v vccreshu , v vccreshd : updated max value ?v vccres hysth : updated test condition table 12: on-resistance : ?i qll : updated max value for out1-6 and typ, min, max for ecfd table 13: power outputs switching times : ?t d on h : updated min value for all out except out 7,8 ?dv out /dt: updated min value table 15: gate drivers for the external power-mos (h-bridge) : ?i pdgshx : removed row ?r ghx , r glx : updated min, typ and max values table 18: open-load monitoring : ?v odsl : added min and max values, updated typ value ?v odsh : added min and max values table 19: electrochrome mirror driver : ? dnl ecv , dnl ecfd : added note table 20: delay time from standby to active mode : ?t set : updated max value table 46. document revision history (continued) date revision change l99dz80ep revision history doc id 18260 rev 5 67/68 16-sep-2011 4 updated table 1: device summary table 9: overvoltage and undervoltage detection ?v suv off : updated min value table 11: charge pump ?v cp : updated test condition and max value ?i cp : updated max value ?i cplim : updated min value table 12: on-resistance ?i qlh : updated min value ?i qll : updated test condition table 13: power outputs switching times ?t d off l : updated max value ?t d hl , t d lh :updated min value table 14: current monitoring ?|i oc1 |, |i oc6 |, |i oc4 |, |i oc5 |: updated max values ?|i old1 |, |i old6 |: updated min value table 15: gate drivers for the external power-mos (h-bridge) ?r ghx , r glx :updated min, typ and max values table 16: gate drivers for the external power-mos switching times ?i ghxrmax , i ghxfmax , di ighxr , di ighxf : updated parameters; updated min, typ and max values ?t ccp : updated max value ?t ccpacc : removed row ? table 17: drain source monitoring : ?v scd1 , v scd2 , v scd3 , v scd4 : updated test contitions, min and vax values ?t scd : updated min, typ and max values ? table 20: delay time from standby to active mode ?t set :updated min, typ and max values table 21: inputs: di, csn, clk, dir and pwmh ?r csn in ,r clk in , r di in , r dir , r pwmh :updated min, typ and max values updated table 27: cross-current protection time 22-sep-2013 5 updated disclaimer. table 46. document revision history (continued) date revision change l99dz80ep 68/68 doc id 18260 rev 5 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems with product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ?automotive, automotive safety or medical? industry domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statem ents and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or register ed trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2013 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - swed en - switzerland - united kingdom - united states of america www.st.com |
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